1. Technical Field
The present invention generally relates to oscillators and, more particularly, to a voltage or current controlled relaxation oscillator using a differential signal.
2. Description of the Related Art
A voltage-controlled oscillator (VCO) is one of the most critical building blocks in phase-locked loop (PLL) design. For digital clock generation, current-starved ring VCOs have been primarily used in monolithic PLLs since they provide a wide tuning range and high integration. See, e.g., Young et. al, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors”, IEEE Journal of Solid-State Circuits, November 1992, the disclosure of which is incorporated by reference herein. Turning to FIG. 1A, a current-starved ring VCO is indicated generally by the reference numeral 100. The current-starved ring VCO 100 includes a plurality of current sources 102 and a plurality of delay elements 105. The oscillation frequency of the current-starved ring VCO is directly related to the delay time of each delay element 105, resulting in high sensitivity to process, voltage, and temperature (PVT) variation. The nonlinear voltage-to-frequency transfer characteristic of the current-starved ring VCO also provides a low VCO gain at high frequencies, which is not desirable in PLL design.
Turning to FIG. 1B, a relaxation oscillator with a grounded timing-capacitor is indicated generally by the reference numeral 140. The relaxation oscillator 140 includes a plurality of current sources 142, the grounded-timing capacitor 144, and a Schmitt trigger 146. Since the oscillation frequency is fully characterized by the current, the capacitor and the reference voltage, it has a good linear-tuning-range. If the capacitor value increases, both the center frequency and the VCO sensitivity decrease with the same proportion. At high speed, however, the delay time of the latch plays a significant role in determining the oscillation period and the performance of the VCO will be degraded. Due to the single-ended structure of the relaxation oscillator 140, a 50% duty cycle and a good supply-noise-rejection cannot be easily obtained. A semi-differential architecture which employs two single-ended VCOs has been proposed to yield a 50% duty cycle and to relax the delay time requirement of the latch at high speed, but it requires two timing capacitors and consumes more power.
Turning to FIG. 1C, a source-coupled relaxation oscillator with a floating timing-capacitor is indicated generally by the reference numeral 180. The source-coupled relaxation oscillator 180 includes a plurality of current sources 182, the floating point timing capacitor 184, and a plurality of transistors 187. The source-coupled relaxation oscillator has poor voltage-to-frequency characteristics mainly due to the nonlinear load transistors. This is even worse in CMOS since the CMOS diode characteristic is not as good as the bipolar diode characteristic. Thus, this architecture is seldom used for CMOS VCOs. Nonetheless, the architecture of the source-coupled relaxation oscillator 180 has several advantages. For example, the source-coupled relaxation oscillator 180 has only one differential stage with the minimum number of the transistors. The simple architecture of the source-coupled relaxation oscillator 180 offers low power consumption and its differential operation provides a 50% duty cycle. Moreover, the source-coupled relaxation oscillator 180 also provides supply noise rejection since the signal is fully differential at zero-time crossing where the jitter performance is mainly determined.
As discussed previously, the arrangement of a relaxation oscillator with a floating capacitor is attractive if it can provide wide linear-range and less sensitivity to process variations at high speed. The main limitation of this arrangement comes from the nonlinear amplitude-dependency on the tail current. A similar technique to that used in ring-oscillator-based VCOs with differential delay cells has been employed to achieve the constant amplitude. See, e.g., the above-reference article by Young et. al, entitled “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors”. By using this technique on the relaxation oscillator with a floating capacitor, the operation becomes very close to that of the oscillator with a grounded capacitor and its limitation becomes very relaxed. Turning to FIG. 2, a programmable relaxation VCO with constant amplitude is indicated generally by the reference numeral 200. The programmable relaxation VCO 200 includes a replica cell 210, a plurality of capacitors C1 through CN, a plurality of transistors M1, M2, M3, M4, and a plurality of adjustable current sources 240. Such an arrangement is further described, e.g., in U.S. Pat. No. 6,377,129, entitled “Programmable Relaxation Oscillator,” and incorporated by reference herein. As shown in FIG. 2, the effective load resistances of M3 and M4 are controlled by the replica cell 210 to maintain a constant voltage swing at nodes A and B. Accordingly, the oscillation frequency is determined in a way similar to the relaxation oscillator with a grounded capacitor but at a comparable power savings, and a 50% duty-cycle can be obtained due to its simple and symmetric structure.